nRF24L01+: 2014

#include <avr/io.h>
#include <stdio.h>
#include <avr/delay.h>
#include "SPI.h"
#define F_CPU 1000000UL
#include <avr/interrupt.h>
//#include "nRF24L01.h"

#define PORT_SPI PORTB
#define DDR_SPI DDRB
#define DD_MISO DDB4
#define DD_MOSI DDB3
#define DD_SS DDB2
#define DD_CE DDB1
#define DD_SCK DDB5

#define W 1
#define R 0

#define CONFIG 0x00
#define STATUS 0x07
#define RF_CH 0x05
#define EN_AA 0x01
#define RF_SETUP 0x06
#define EN_RXADDR 0x02
#define SETUP_AW 0x03
#define SETUP_RETR 0x04
#define RX_ADDR_P0 0x0A
#define TX_ADDR 0x10
#define RX_PW_P0 0x11

#define R_REGISTER 0x00
#define W_REGISTER 0x20
#define R_RX_PAYLOAD 0x61
#define W_TX_PAYLOAD 0xA0
#define FLUSH_TX 0xE1
#define FLUSH_RX 0xE2
#define NOP 0xFF
void spi_init()
//inicializacion de la comunicacion SPI
{

DDR_SPI |= ((1<<DD_MOSI)|(1<<DD_SS)|(1<<DD_SCK)|(1<<DD_CE));
SPCR |= (1<<SPE)|(1<<MSTR); // SPI Enable y Master/Slave select
//(0<<SPIE)| // SPI Interupt Enable
//(0<<DORD)| // Data Order (0:MSB first / 1:LSB first)
//(0<<SPR1)|(1<<SPR0)| // SPI Clock Rate
//(0<<CPOL)| // Clock Polarity (0:SCK low / 1:SCK hi when idle)
//(0<<CPHA)); // Clock Phase (0:leading / 1:trailing edge sampling)
//SPSR = (1<<SPI2X); // Double Clock Rate
PORTB|= (1<<PORTB2);
PORTB&= (0<<PORTB1);
}

char WByteSPI(unsigned char dato){
SPDR = dato;
while(!(SPSR & (1<<SPIF)));
return SPDR;
}

uint8_t LeerReg(uint8_t reg){
_delay_us(10);
PORTB&= (0<<PORTB2);
_delay_us(10);
WByteSPI(R_REGISTER + reg);
_delay_us(10);
reg=WByteSPI(NOP);
PORTB|= (1<<PORTB2);
return reg;
}

void EscribirReg(uint8_t reg, uint8_t paquete){
_delay_us(10);
PORTB&= (0<<PORTB2);
_delay_us(10);
WByteSPI(W_REGISTER + reg);
_delay_us(10);
WByteSPI(paquete);
_delay_us(10);
PORTB|= (1<<PORTB2);
}

uint8_t *WtoNrf(uint8_t RW, uint8_t reg, uint8_t *val, uint8_t n)
{
if (RW == W)
{
reg = W_REGISTER + reg;
}

static uint8_t ret[32];

_delay_us(10);
PORTB&= (0<<PORTB2);
_delay_us(10);
WByteSPI(reg);
_delay_us(10);

int i;
for (i=0; i<n; i++)
{
if ((RW == R) && (reg != W_TX_PAYLOAD))
{
ret[i]=WByteSPI(NOP);
_delay_us(10);
}
else
{
WByteSPI(val[i]);
_delay_us(10);
}
}
PORTB|= (1<<PORTB2);
return ret;
}

int main(void)
{
uint8_t val[5];
uint8_t *data;
int i=0;
DDRD=255;

// Inicializa SPI
spi_init();

_delay_ms(500);
val[0]=0x01;
WtoNrf(W,EN_AA,val,1);
WtoNrf(W,EN_RXADDR,val,1);
val[0]=0x03;
WtoNrf(W,SETUP_AW,val,1);
val[0]=0x01;
WtoNrf(W,RF_CH,val,1);
val[0]=0x07;
WtoNrf(W,RF_SETUP,val,1);
for(i=0; i<5; i++)
{
val[i]=0x12;
}
WtoNrf(W,TX_ADDR,val,5);
val[0]=5;
WtoNrf(W,RX_PW_P0,val,1);
val[0]=0x2F;
WtoNrf(W,SETUP_RETR,val,1);
val[0]=0x1E;
WtoNrf(W,CONFIG,val,1);
_delay_ms(100);

//uint8_t write[5];
//for(i=0; i<5; i++)
//{
//write[i]=0x93;
//}
//WtoNrf(R,FLUSH_TX,write,0);
//WtoNrf(R,W_TX_PAYLOAD,write,5);
//_delay_ms(15);

data= WtoNrf(R,CONFIG,data,2);
PORTD = data[1];
_delay_ms(1500);
PORTD = 0;
_delay_ms(1000);

data= WtoNrf(R,RF_CH,data,1);
PORTD = data[0];
_delay_ms(1500);
PORTD = 0;
_delay_ms(1000);

while(1)
{
//TODO:: Please write your application code
}
}

lunes, 24 de marzo de 2014